Numerical Analysis of Vertical Double Gate MOSFETs (VDGM) With Dielectric Pocket (DP) Effects on Silicon Pillar for Nanoscale Transistor

摘要

Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGMDP indicates a reasonable value of threshold voltage (VT), drive and off -leakage current (ION and I_(OFF)), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current I_(Dsat) due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously.