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Analysis and Design of Fully Differential Gain-Boosted Op-amp for 14bit 100MS/s Pipelined Analog-to-Digital Converter

机译:14位100ms / S流水线模数转换器的全差分增益促进OP-AMP的分析与设计

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This paper presents the analysis and design of high speed, high gain fully differential operational amplifier (op-amp). The op-amp is designed for sample and hold circuit of 14 bit 100MS/s pipelined analog-to-digital converter (ADC). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitance common mode feedback circuit. The boosting op-amp is connected as a follower. The op-amp is designed in 0.18μm CMOS process with 3.0V power supply. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.
机译:本文介绍了高速,高增益全差分运算放大器(OP-AMP)的分析和设计。 OP-AMP专为14位100ms / S流水线模数转换器(ADC)的样本和保持电路而设计。主运算放大器和升压运算放大器都是完全差分的折叠共级码。主OP-AMP具有开关电容共模反馈电路。升压运算放大器连接为跟随器。 OP-AMP采用0.18μm的CMOS工艺设计,具有3.0V电源。幽灵仿真表明,OP-AMP具有112dB的直流增益和1.15GHz的Unity Gain带宽。

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