Advanced Metrology For Beyond Silicon Semiconductor Device Structures

摘要

In order to continue CMOS scaling for the 7 nm node and below, the integration of advanced semiconductor materials such as Germanium (Ge) and III-V compound semiconductors (InP, InGaAs, InAlAs) is indispensable [1]. This is mainly due to the fact that charge carriers inside the latter materials exhibit significantly lower effective masses and hence offer enhanced mobility and injection velocity values in comparison with silicon (Si). This in turn facilitates the fabrication of transistors with increased performance. Although Ge and III-V compound materials can be grown epitaxially on Si substrates to date, the large differences in lattice constant and material characteristics typically lead to very high defect densities in these layers, causing a degradation of the material properties and hence device performance. For this reason, a qualitative and quantitative assessment of the defectivity of such layers is of utmost importance. Moreover, controlling layer parameters such as thickness, composition, crystalline quality and strain becomes more and more difficult but at the same time also more demanding. Although transmission electron microscopy (TEM, in combination with EDX, NBD) has emerged as a very sophisticated metrology tool capable of determining the above mentioned parameters, the complexity (i.e. measurement time) as well as the destructive nature of the technique limit its application during process development and in an actual fab environment. Moreover, it is important to note that due to its high spatial resolution TEM can visualize individual crystalline defects in great detail, however, the reduced specimen size and the limited field of view hamper the assessment of defect densities below ～1e8 cm~(-2).