Due to the increased number of on- chip transistors from VLSI technology scaling, temperature rise and variation within a chip increase rapidly beyond 65 nm technology node. The worst-case power and performance at hot spots limit the overall chip performance. This work uses a non-gray model based on the phonon Boltzmann transport equation (BTE) to compute the temperature rise and distribution in a nano-scale multi-finger asymmetrical double-gate FinFET clock buffer. The BTE simulation is used in the device channel regions to accurately account for phonon boundary scattering and phonon confinement, while the Fourier heat conduction equation is employed in other regions of the device such as the silicon substrate, buried oxide and metal interconnects. Non-uniform Joule heating by electron-phonon scattering is calculated from the dot product of the electric field and the current density from numerical device simulations using TAURUS. The computed results for non-uniform Joule heating are compared with those based on uniform Joule heating, for different percentages of energy release in the optical phonon mode. The simulation results reveal that the maximum junction temperature rise obtained by the BTE simulations with non-uniform Joule heating is much higher than that obtained from the uniform Joule heating if zero optical phonon group velocity is assumed, while the average junction temperature rise is about the same for both cases. With the assumption of zero optical phonon group velocity, simulation results with 100%, 85%, 60%, 35% and 0% of the Joule heating in the optical phonon mode show that the more Joule heating is deposited into optical phone mode, the higher is the junction temperature rise. However, if non-zero optical phonon group velocity is assumed, the maximum junction temperature rise predicted is not significantly higher than the Fourier prediction. This indicates that previously published models which do not account for optical mode group velocity may need to be reconsidered.
展开▼
