Study of surface roughness and dislocation generation in strained Si layers grown on thin strain-relaxed buffers for high performance MOSFETs

摘要

Epitaxial growth of Si over a strain relaxed buffer (SRB) of SiGe can enhance MOSFET performance through increased carrier mobility in tensile strained Si. However, device self-heating due to the low thermal conductivity of SiGe remains a major obstacle to realising the advantages offered by strained Si technology. Thin SRBs seek to overcome this issue and improve the economical viability of SRBs through faster growth time and reduced material consumption, while maintaining the benefits of increased carrier mobilities. Several methods for generating thin SRBs have been proposed but to date their thermal stability has not been established. Evaluating surface roughness is critical as it impacts device performance at high vertical fields, thus its influence increases at advanced technology nodes. Since surface roughness is highly dependent on epitaxial growth method, it is inevitable that surface roughness of thin SRBs will differ from that of conventional thick SRBs. Increasing the Si channel thickness can mitigate the degradation in electrical performance due to Ge out-diffusion from the SRB into the Si channel during high temperature device fabrication. Channel macrostrain can be partially sustained in Si channel layers exceeding the critical thickness on thin SRB material. However the resilience of surface morphology in the structures following thermal processing must also be confirmed before thin SRBs can be considered for devices. In this work the impact of high temperature annealing typical of CMOS processing on the surface morphology of thin SiGe SRBs is investigated for strained silicon layers above and below the critical thickness.