DEVELOPMENT METHODOLOGY FOR fflGH-K GATE DIELECTRICS ON in-V SEMICONDUCTORS: Ga2O3 TEMPLATE ON GaAs

摘要

A comprehensive methodology for the development of gate dielectrics on III-V semiconductors is proposed. This methodology has been motivated by the tremendous difficulties encountered during the development of gate dielectrics on GaAs. The understanding that modern gate dielectrics are typically layered structures with the immediate dielectric/semiconductor interface having substantially different (and often mutually exclusive) requirements compared to the bulk of the dielectric film in terms of materials, manufacturing, and suitable characterization techniques, is at the core of the proposed methodology. While capacitor based characterization methods such as capacitance-voltage (C-V) measurements which require to maintain quasi-equilibrium in the semiconductor remain an essential component, recombination based techniques such as photoluminescence intensity (PL-I) have become a necessary ingredient for gate dielectric development on wider bandgap semiconductors. Based on the exemplary system of a Ga2O3 template on GaAs, the feasibility of PL-I and C-V techniques for characterization of oxide template/semiconductor interfaces is discussed. Recombination based techniques such as PL-I have been found to be superior for oxide template/semiconductor interface characterization.