Development methodology for high-κ gate dielectrics on Ⅲ-Ⅴ semiconductors: Gd_xGa_(0.4-x)O_(0.6)/Ga_2O_3 dielectric stacks on GaAs

摘要

A three step methodology for the development of gate dielectrics on Ⅲ-Ⅴ semiconductors including atomistic interface studies, oxide template formation, and dielectric stack manufacturing has been proposed. The third and final step encompasses the realization of high-κ Gd_xGa_(0.4-x)O_(0.6)/Ga_2O_3 dielectric stacks on GaAs. This article reports high-κ stacked gate oxides with an oxide relative dielectric constant of 20.8±1, a breakdown field exceeding 4 MV/cm, leakage currents of ≈2 X 10~(-8) A/cm~2 at an electric field of 1 MV/cm, and a broad minimum of interface state density D_(it) ≤ 2 X 10~(11) cm~(-2) eV~(-1) on n-type GaAs suggesting a U-shaped D_(it) distribution. The proposed methodology can potentially be extended to high-κ gate dielectric development on elemental semiconductors such as Si and Ge and wide band gap semiconductors such as GaN.