As the I/O count, clock rate and power dissipation continue to increase on high-end processors, traditional flip chip on build-up carriers become more and more problematic. Although the build-up substrates have been able to continue to lower feature sizes, the solder bump and the mating solder pad on the substrate have not kept up. One approach to eliminating the pitch limitations of solder bumps is to replace the solder bump with micro-vias in the buildup interconnect structure, directly connecting to the chip pads. This can be accomplished by embedding the chips within a multilayer build-up structure using low CTE dielectrics and laser formed micro-vias. Today, laser formed micro-vias are capable of connecting to up 8000 chip pads on a 100 micron array pitch, far beyond solder bump capability. As a result of the flexibility to accommodate a very fine I/O pitch on the die, this technology can accept either area array or perimeter I/O configurations having pitches as low at 100 micron, as a result of the improvements in laser drilling technology and high accuracy placement equipment. This paper will describe the leading bump-free embedded chip technology, overview process steps, present thermal stress models, and reliability data.
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