A Novel approach for Dual Damascene Trench Etch for 90 nm Low-k Interconnect with No Middle Etch Stop Layer

摘要

In this paper, a novel dual damascene (DD) trench etch process on 90 nm no middle etch stop layer (ESL) low-k inter metal dielectric stack is discussed. As technology advances, it becomes desirable to remove the middle ESL to obtain a lower effective k value in order to improve interconnect performance. This raises great challenges especially to etch area in order to get repeatable process with good profile and free of defects such as fence or via corner chopping. Here, a via first dual damascene scheme and via-fill and etch back process flow are combined to get a successful DD trench patterning integration approach. This leaves a relative uniform BARC layer all over the wafers prior etch and facilitate the subsequent etch process. The DD trench patterning process flow is shown in Fig.1. Trench etch front and the level of the via-filling material control are essential during whole DD trench etch process to avoid physical defects, such as fence, via corner chopping or even gouging. A designed etch chemistry and a unique via-filling material recess step are applied together to obtain the desired profile with excellent trench depth control as shown in Fig.2. An in-situ interferometric system, iRM, is used to monitor the trench depth and control the etch time to achieve the preset depth. It much reduces the depth variation from layer to layer shown in Fig.3 as well as wafer to wafer variation. Good electrical results on up to four-layer metal via chain resistance and meander continuity are shown in Fig.4 to confirm the feasibility of this scheme.