Dual Damascene copper interconnects with low-k polymer dielectrics.

摘要

To increase the speed of integrated circuits (ICs), copper interconnects combined with low dielectric constant (low-k) insulators are accepted as the near future replacements for traditional aluminum and silicon dioxide based interconnect technology. In this work, multilevel copper interconnects and low-k polymer insulator fabrication strategies are investigated, with emphasis on integration and two-level metal process realization.; Copper interconnects were fabricated with dual Damascene patterning of etching vias and interconnect trenches in the insulator followed by metal deposition and chemical mechanical polishing (CMP) to remove the excess material. The copper adhesion layer and diffusion barrier (or liner) material used was sputtered tantalum. The low-k dielectrics used were vapor deposited parylene-n (PA-n) and spin-on CycloteneTM 5021 divinylsiloxane bisbenzocyclobutene (BCB). PECVD silicon nitride was used as a hard etch mask for dielectric etching, as well as a CMP polish stop, a plasma etch stop and copper diffusion barrier.; The dual Damascene processing strategies used to create the via and interconnect pattern were investigated at length. Full integration was performed with four traditional dual Damascene strategies, followed by the development of two unique “clustered hard mask” strategies with full integration of one of them. The fabrication and characterization of dual Damascene copper interconnects led to the defining of eight dual Damascene optimization criteria, specifically addressing polymer dielectrics. Based on polymer dielectric processing considerations and electrical measurements, the clustered hard mask strategies were determined to be superior in comparison to the dual Damascene strategies previously developed for oxide-based dielectrics.; The two-level interconnects were characterized by focused ion beam (FIB) cross sectioning and imaging to validate the success of the dual Damascene integration. The average metal-to-metal specific contact resistance was 5 × 10−9 Ω-cm2 for 2–6μm square vias, and as low as 1–3 × 10−9 Ω-cm 2 for 2μm square vias. These specific contact resistance values are comparable to previous dual Damascene integration results with oxide dielectric. The magnitude of the electrical line width bias was consistent with the relative merits of each dual Damascene process.