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Stress and dopant activation in solid phase crystalized Si films

机译:固相结晶Si薄膜中的应力与掺杂剂活化

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Defect creation mechanisms during solid phase crystallization (SPC) of Si thin films were investigated with PECVD amorphous precursor samples produced with various deposition temperatures and thicknesses. These precursor films were implanted withdopant and then crystallized to obtain both SPC and dopant activation. The doping efficiency was found to decrease with the tensile stress level as measured by Raman shift. The stress shows a decrease as the precursor deposition temperature and thicknessare lowered. Furthermore, a lower level of stress is induced by rapid thermal annealing when the annealing temperature is high enough to soften the glass substrate on which the films were deposited. We show that by control of stress during the SPC step,intragrain defect density can be lowered and electronic quality of the resulting polycrystalline Si films can be improved. Based on these observations, we propose the following tentative model to explain the defect creation: during SPC, tensile stressevolution is considered to result from the volumetric contraction of Si film when it transforms from the amorphous to crystalline phase. This contraction is retarded by the substrate, which imposes a tensile stress on the film. A high level of stressleads to formation of structural defects inside the grains of the resulting polycrystalline material. These defects trap carriers or complex with the dopant reducing doping efficiency.
机译:用各种沉积温度和厚度产生的PECVD非晶前体样品研究了Si薄膜的固相结晶(SPC)期间的缺陷生成机制。将这些前体膜植入掺杂物,然后结晶以获得SPC和掺杂剂活化。发现掺杂效率随着拉曼偏移测量的拉伸应力水平而降低。应力显示出随着前体沉积温度和厚度降低的降低。此外,当退火温度足够高以软化沉积薄膜的玻璃基板时,通过快速热退火诱导较低水平的应力。我们表明,通过在SPC步骤期间控制应力,可以降低腔内缺陷密度,并且可以提高所得的多晶Si膜的电子质量。基于这些观察,我们提出了以下暂定模型来解释创造的缺陷:在SPC期间,考虑拉伸胁迫性能是由Si膜的体积收缩来引起,当它从非晶相转化到结晶相时。基材延迟了这种收缩,这在薄膜上施加了拉伸应力。高水平的应力线,形成所得多晶材料晶粒内的结构缺陷。这些缺陷陷阱载体或复合物,掺杂剂降低了掺杂效率。

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