Defect reduction strategy for plasma etch

摘要

Plasma etch has always played an important role in microelectronic manufacturing. Defects observed at post-etch usually have significant impact on yield. The visual post-etch defects are generally divided into three major categories. Those defects discovered at etch but not generated by etch, the defects generated during etch, and the defects generated by interaction between different process layers. The prior layer defects are the defects uncovered by the etch process but originated in prior layers such as film or lithography. The true plasma etch-generated defects usually consist of process-induced defects and equipment defects. Process integration defects are those type of defects that are caused by interaction between different layer stoichiometry and process chemistry. The origin of these defects observed at post-etch need to be identified and isolated in order to make defect reduction in the plasma etch area manageable. The best defect yield management strategy is to use an integrated monitoring scheme consisting of in-line, short-loop, and equipment monitor wafers to monitor defect levels in the production line and to troubleshoot yield loss caused by defects. This paper discusses how to set up effective integrated short-loop patterned etch and blank resist-coated etch equipment monitors to isolate the contribution of different components of post-etch defects listed above.