Trench Etching Effects on Shallow Trench Isolation (STI) Electrical Properties for Sub-0.25 #mu#m CMOS Devices

摘要

Based on a modified STI scheme (trench filled with HDP-CVD oxide, planarized by high specification CMP, and with additional trench corner rounding process), the effects of trench etching process, which defines trench slope, on the performance of isolation, junction leakage, and I_d-V_g characteristics, are studied. The examined slope range is between 65deg and 83deg. In all cases, subthreshold double hump were not observed. Isolation and junction leakage are found to be independent of the trench slope. Excellent narrow width effect is demonstrated for all of the studied STI structures. The threshold voltage (V_t) varies by less than 60 mV and 10 mV when the transistor width is reduced from 10 #mu#m down to 0.3 #mu#m for NMOS and for PMOS, respectively. The results show the modified STI scheme is a robust way for sub-quarter-micron isolation technology.