Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

摘要

In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the SID region. Silicide can be used to further reduce the active resistance.