Gate-last integration on planar FDSOI for low-V_(Tp) and low-EOT MOSFETs

摘要

We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg = 15 nm and active widths of W = 80 nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of V_(Tp) = 0.2 V and one decade gate current (J_G) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (V_(FB)) shift under stress.