首页> 外文会议>Conference on Optoelectronic and Microelectronic Materials And Devices Proceedings >Characteristics of 0.1 /spl mu/m Si MOSFETs with ISRC (Inverted-Sidewall Recessed-Channel) structure for reduced short channel effect
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Characteristics of 0.1 /spl mu/m Si MOSFETs with ISRC (Inverted-Sidewall Recessed-Channel) structure for reduced short channel effect

机译:具有ISRC(倒侧壁凹槽)结构的0.1 / SPL MU / M SI MOSFET的特性,用于减少短沟道效应

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To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quarter-micrometer MOSFETs, we have fabricated a 0.1 /spl mu/m recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel) and verified its superiority. The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m. The maximum transconductance at V/sub D/=2.0 V is 455 mS/mm for nMOSFET and 191 mS/mm for pMOSFET. The DIBL (Drain Induced Barrier Lowering) is kept within 70 mV from V/sub D/=0.1 V to V/sub D/=2.0 V for both devices. By the comparison with the conventional MOSFET, the reduction of short channel effects is demonstrated. By simulation, it is verified that this results from the laterally non-uniformly doped channel profile.
机译:要解决短信道效应与次季度微米MOSFET的性能增强之间的权衡问题,我们制造了一个0.1 / SPL MU / M嵌入式通道MOSFET结构,称为ISRC(倒侧壁凹槽)和验证了其优越性。氧化物厚度为4nm,有效通道长度为0.1 / spl mu / m。 V / Sub D / = 2.0 V的最大跨导是NMOSFET的455ms / mm,为PMOSFET为191 ms / mm。 DIBL(漏极感应屏障降低)在两个设备的V / SUB D / = 0.1V至V / SUB D / = 2.0V中保持在70mV内。通过与传统MOSFET的比较,证明了短信效应的减少。通过仿真,验证了这导致横向不均匀掺杂的沟道轮廓。

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