Chip embedding technology developments leading to the emergence of miniaturized system-in-packages

摘要

At PCB manufacturing level, 50 µm thin chips have been embedded with pitches up to 200 µm in up to 18″×24″ panels using face-down technology for chip assembly. This paper describes in detail the merits and shortcomings of both face-down and face-up embedding. In addition, it shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches up to 50µm. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400µm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100µm pitch. All Embedded chip-QFN packages have been manufactured in 10″×14″ panels at prototype level. This paper also shows the latest developments in semi-additive processes for copper structuring of chip embedded packages with pitches lower than 100µm. Ultra fine line structuring technology has been developed up to 15µm L/S copper structures using innovative 2µm copper base foils. Qualitative analysis using acoustic microscopy and shear testing of the QFNs provides evidence of good resin adhesion and package mechanical robustness. Furthermore, this study shows promising results for embedding of chips with pitches dwon to 50µm, introducing a new “vialess” face-down embedding approach where direct contacts are established between copper pads and functional copper foil. Developmental work on “vialess” embedding technology is still ongoing.