New Capacitorless Dynamic Memory Compatible with SOI and Bulk CMOS

摘要

We introduce a capacitorless DRAM cell based on a multibody transistor concept. The device features a body partitioning with dedicated regions for hole storage and electron current sensing. This separation allows aggressive scaling beyond the limits imposed by the supercoupling effect. The cell is fully compatible with both standard bulk and Silicon On Insulator substrates without changes in its architecture. Numerical simulations demonstrate its performances in terms of 1T-DRAM operation, current margins and retention time.