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首页> 外文期刊>Electron Devices, IEEE Transactions on >Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates
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Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates

机译:适用于22-nm节点的新型无电容器1T-DRAM单元,兼容大块和SOI衬底

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摘要

A new concept of multibody single-transistor dynamic-random-access-memory cell fully compatible with both standard bulk and silicon-on-insulator substrates is presented. Its novelty comes from the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction), which define a body partitioning for hole storage and current sense. The charge accumulated in the top body controls the current flowing through the bottom body. The scalability is ensured due to the suppression of the supercoupling effect, thus allowing the coexistence of electrons and holes in very thin transistors. Numerical simulations of electrostatics and dynamic operation show how the transient response of this device can be used for dynamic-memory applications, achieving attractive performance in terms of state discrimination and retention time in very scaled devices.
机译:提出了与标准体衬底和绝缘体上硅衬底完全兼容的多体单晶体管动态随机存取存储器单元的新概念。它的新颖性来自两个具有相反掺杂极性(即p-n结)的硅膜的并置,它们定义了用于空穴存储和电流检测的主体分区。积累在顶部主体中的电荷控制流过底部主体的电流。由于抑制了超耦合效应,因此确保了可伸缩性,从而允许电子和空穴在非常薄的晶体管中共存。静电和动态操作的数值模拟表明,该器件的瞬态响应可如何用于动态存储器应用,在非常规模化的器件中,在状态识别和保留时间方面实现了诱人的性能。

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