Wafer-Level Integration Technology with Heterogeneous Chip Redistribution and Inter-Chip Layer Process

摘要

The authors have proposed a pseudo-SOC (System on Chip) technology, a novel integration technology forming inter-chip layer with semiconductor process techniques on a chip-redistributed wafer with heterogeneous device chips encapsulated with inter-chip resin. This is a novel integration technology realizing a thinned package structure with fine inter-chip layer, unattainable with the previous SIP (System in Package) technology and integration of heterogeneous devices unattainable with the previous SOC technology. A stress analysis for realizing a pseudo-SOC structure for minimizing the strain in the integrated chips was carried out. A pseudo SOC with narrow gap and thinned structure was fabricated. An RF-receiver was also demonstrated using pseudo-SOC technology and the integration density was confirmed to be 16 times higher than the conventional SIP technology.