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NBTI Effects in pMOSFETS with TiN/Hf-Silicate Based Gate Stacks

机译:与基于锡/ HF硅酸盐的栅极堆叠的PMOSFET中的NBTI效应

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Effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi{sub}xO{sub}y (20% SiO{sub}2) based high-κgate stacks are studied under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔV{sub}T) is most probably due to the mixed degradation within the bulk high-κ.For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔV{sub}T in our devices conform to SiO{sub}2 based reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures higher Si-H bond-annealing/bond-breaking ratio, due to the experimentally observed absence of the impact ionization induced hot holes at the interracial layer (IL)/Si interface, probably limits the interface state generation and ΔV{sub}T as they quickly tend to saturate.
机译:在不同的栅极偏压和高温条件下,研究了具有锡/ HFSI {Sub×XO {Sub} Y(20%SiO {Sub} 2)的高κ·y(20%SiO {Sub} 2)的P沟道MOSFET的影响。对于低偏置条件,阈值电压移位(ΔV{Sub} T)最可能是由于散装高κ内的混合劣化。对于中等高偏压条件,在孔的存在和随后的扩散存在下的H型解离最初负责接口状态和正电荷的批量陷阱生成。我们的装置中ΔV{Sub} T的初始时间,温度和氧化物电场依赖性符合NBTI的SiO {Sub} 2反应扩散(R-D)模型。在高温下的高偏压条件下,较高的Si-H键退火/粘合率/粘合比,由于实验观察到侵入电离诱导的异形层(IL)/ Si接口的热孔,可能限制界面状态和ΔV{sub} t,因为它们很快倾向于饱和。

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