Flip-Chip-to-Wafer Stacking: Enabling Technology for Volume Production of 3D System Integration on Wafer Level

摘要

A continuous demand for electronic devices with more advanced functionality, in addition to decreased size and weight calls for ever-increasing integration and complexity. 3D system integration using flip-chip-to-wafer stacking offers the highest integration and performance of chip technology in combination with the flexibility and time-to-market advantages of packaging technology. Fundamental benefits of flip-chip-to-wafer stacking are the possibility to combine chips from a broad range of process technologies and wafer sizes and the integration of multiple, different-sized chips onto a single base chip. In this paper we describe a process flow and manufacturing technology called Advanced-Chip-to-Wafer technology (AC2W technology) suitable for volume production of chip-to-wafer stacks with different 3D interconnect types and how it can be applied to 3D system integration and other technologies such as MEMS packaging. We discuss in detail the advantages and limitations of this technology and the challenges facing the die- and the newly developed chip-to-wafer bonder. Finally, we report results for a specific 3D interconnection type as an application example.