Vertical Integration of RF Passive Components in Stacked Wafer-Level Packages

摘要

Electrical performance of via-connected rectangular spiral inductors integrated on a low-loss spacer substrate and thus vertically-spaced above a lossy silicon substrate is analyzed using 3D electromagnetic simulation tool Ansoft HFSS with a goal to identify the optimum via-interconnect scheme. The results show that vertically spaced spiral inductors with a properly designed via-interconnect scheme is a viable option to achieve high-quality passives and to minimize chip area of silicon RF ICs. Improperly designed electrical via interconnect can severely degrade electrical performance of spiral inductors due to the in-via induced eddy currents and/or parasitic capacitances. Smaller via diameters and their larger separations are preferable to minimize parasitic capacitances. The optimum via length (i.e. spacer substrate thickness) is in the range of 100-200 μm, when the influences of a lossy silicon substrate and via capacitances are minimized.