ATOMIC-LAYER DEPOSITION OF ULTRATHIN SILICON NITRIDE FOR SUB-TUNNELING GATE DIELECTRICS

摘要

n-MOSFETs with atomic-layer-deposited silicon-nitride gate dielectrics (EOT=2.3nm) were fabricated. Slightly smaller electron mobility was obtained for the silicon-nitride gate dielectrics than that for the reference SiCh gate dielectrics (Tox=1.8nm). However, hot-carrier-induced threshold voltage (Vu,) shift in the transistors with the silicon-nitride gate dielectrics was found to be less than that in the SiO2 transistors. Taking the reduced leakage current, suppressed boron penetration, better TDDB characteristics, soft breakdown-free phenomena, and reduced mobility degradation for the silicon nitride (reported previously) into account, atomic-layer-deposited silicon-nitride gate dielectrics are very promising for sub-100-nm technology.