Low-Power and High-Speed Hf-based gated CMOS FET with Dual Poly-Si Gate Electrodes

摘要

We have developed low power and high speed Hf-based gated CMOSFET with dual poly-Si gate electrode. It is essential to suppress electron traps, which degrade mobility in high-k gate dielectric. A large Vth shift of PFET is observed for poly-Si/high-k gate stacks. A symmetrical set of Vth's for NFET and PFET was realized by channel engineering. Poly-Si/HfSiO gate-stacked CMOS devices have shown low Ioff(N/PFET: 4.8/3.6pA/μm) and high Ion(N/PFET: 469/140 μA/μm), respectively. Moreover, we have newly developed low-gate-bias FET measurement technique for TDDB lifetime estimation by using an emission microscope. We have experimentally confirmed sufficient reliability for practical usage (TDDB lifetime: more than 10 years at 85°C and 1.1 V).