Direct Source-to-Drain Tunnelling and its Impact on the Intrinsic Parameter Fluctuations in nanometre scale Double Gate MOSFETs

摘要

The conventional MOSFETs are likely to reach scaling limitations at gate lengths between 15 and 10nm. The double-gate MOSFET architecture is a promising candidate for scaling to 10nm and below in line with the requirements of the International Technology Roadmap. However, it is expected that direct source-drain tunnelling would be a major limiting factor in the double-gate device. In this paper we study, using carefully calibrated density gradient simulations, the impact of quantum confinement and tunnelling on the operation of nanometer scale double gate MOSFETs. We show that source-drain tunnelling is unlikely to be a major effect limiting the scaling of the double gate MOSFET design. We also investigate the influence of source-drain tunnelling on the intrinsic parameter fluctuations in these devices.