High Performance CMOS on SOI

摘要

This paper describes the recent progress in the development of high performance CMOS on SOI at IBM. In 1999 Assaderaghi [1] had reviewed the IBM SOI technology from a global perspective ranging from SOI material selection to circuit styles adapted for designing in partially depleted (PD) SOI. The focus of this paper will be on the development aspects that support the aggressive scaling of CMOS transistors on SOI.