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CVD Tungsten Via Void Minimization for Sub 0.25 μm Technology

机译:CVD钨通过空隙最小化为0.25μm技术

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摘要

The mechanism of void formation in tungsten plugs during W CVD process is analyzed qualitatively and analytically. A simple mathematical model for W plug fill is presented for order of magnitude analyses. The model is shown to make good "relative" predictions for process pressure and temperature to be used to fill various aspect ratio contacts. The electrical data shows that contacts with smaller voids result in lower via chain and Van der Pauw resistances.
机译:定性和分析分析W CVD工艺期间钨塞中空隙形成的机制。对于幅度分析的顺序,提出了一种简单的W插头填充数学模型。该模型被示出为用于填充各种纵横比触点的过程压力和温度的良好“相对”预测。电气数据显示,具有较小空隙的触点导致较低的通孔链和范德波坑电阻。

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