Dishing reduction for STI-CMP by inserting polysilicon buffer layer

摘要

Shallow Trench Isolation (STI) is a key technology for 0.25um devices and beyond and cannot be manufactured without the use of Chemical mechanical Polishing (CMP)~([1]). Unfortunately, a trench oxide dishing is usually found after CMP, especially for the wide trench. In this paper, we present a new planarization technique that employs an additional polysilicon layer on top of the nitride layer. Such additional polysilicon layer will eventually produce humps at the oxide areas that serve to cushion the dishing effect. In this work, we studied the evolution of step height, film thickness and uniformity throughout the CMP procss, using both test structures and SRAM structures. Comparison among the newly proposed scheme and the conventional process were also presented. Post-CMP performance was characterized in terms of dishing, within wafer uniformity, and surface roughness. A tremendous improvement in dishing and non-uniformity were achieved using the new polysilicon STI scheme.