Yield Analysis of CMOS ICs

摘要

The production yield of CMOS logic ICs in stable process technologies is limited by spot defects due to contaminations. In this paper, experimental results are presented on defect-related failures of SRAM monitor circuits, and simulation methods for failure analysis and yield modeling are introduced. -In analog (CMOS circuits yield loss is mainly due to parametric failures, requiring careful investigations on device matching. -For low power low voltage CMOS logic, a high sensitivity to the statistical variation of the threshold voltage was found. This will get increasing importance for future technologies with reduced supply votlage.