Amorphous silcion thin-film transistors (a-Si:H TFTs) are important driving elements in a variety of applications such as in large area imaging and active matrix liquid crystal displays. However, the reverse lakage current and parasitic capacitance in the a-Si:H TFT leads to adverse effects on its performance. It is ell known that the gate-to-source (Cgs) and gate-to-drain (Cgd) parasitic capacitances in the a-Si:H TFT consist of both geometric and bias-dependent components. The former is due to geometric overlapping between gate and source/drain electrodes and the latter due to charge transport by virtue of the gate-drain electric feidl. We previously reported the formation nof a parasitic p-i-n diode at the drain region that is highly reverse baised for positive drain and negative gate voltages (1). It is this reverse biased p-i-n diode that is the main consituent for leakage and which influences Gas and Cgd in the TFT. IN addition, Cgs is affected by hole conduction through the reverse biased p-i-n diode. In this paper, it is shown, through systematic experimental studies, that the capacitances and leakage current vary consistently with overlap length, gate and drain bias, effective channel length and the a a-Si:H layer thickness.
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