New delay model for 0.5/spl mu/ CMOS ASIC

摘要

As silicon geometry moves closer to deep sub-micron (smaller than 0.5-/spl mu/m) technology, new physical phenomena start to appear and dominate the delay through an ASIC cell. As delays become smaller and the overall performance of applications increase, the emphasis on delay calculation accuracy increases. The authors demonstrate 0.5-/spl mu/m CMOS delay related physical phenomena such as coupling and shielding effects. They show how these components affect the cell and interconnect delays. The effects of these physical phenomena on CAD technology are discussed. A delay model for 0.5-/spl mu/m CMOS ASIC technology is described. This model takes into consideration the following items: unique 0.5-micron physical phenomena; optimization of ASIC library cell characterization time; speed of delay calculator CAD tool; the requirement of interconnect extraction and calculation accuracy; and the extensibility and flexibility of the model to provide additional accuracy for future silicon technology.