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Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits

机译:深层亚微米CMOS电路电源网络电感和电阻开关噪声的估算

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In this paper, we propose an event-driven simulation based approach to estimate the worst case IR drop and Ldi/dt inductive noise an the power supply network. The switching noise is modeled as a weighted sum of the switching currents and the rates of change of the switching currents, where the weights are respectively the effective resistance and inductance (on the P/G network) experienced by each switching current. Monte Carlo and genetic algorithm are employed to search for the worst case input vector pair(s) that induce the maximum switching noise. The worst case input patterns are used in the SPICE simulation to verify the switching noise waveforms on the power supply network. Experimental results show that the worst case switching noise on the power supply network for ISCAS85 benchmark circuits implemented in TSMC 0.25 /spl mu/m technology can be as high as 40% of the supply voltage V/sub dd/.
机译:在本文中,我们提出了一种基于事件驱动的模拟方法来估计最坏情况IR下降和LDI / DT电感噪声成为电源网络。开关噪声被建模为切换电流的加权和和切换电流的变化率,其中重量分别是每个开关电流所经历的有效电阻和电感(在P / G网络上)。 Monte Carlo和遗传算法用于搜索诱导最大开关噪声的最坏情况的输入向量对。最坏的情况输入图案用于SPICE仿真,以验证电源网络上的开关噪声波形。实验结果表明,TSMC 0.25 / SPL MU / M技术中实现的ISCAS85基准电路电源网络上最坏情况的最坏情况的开关噪声可以高达电源电压V / SUB DD /的40%。

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