For the Cu/low-k interconnect process, leakage reliability is an essential item in conjunction with electromigration. We described for the first time Cu intra level leakage deterioration through vias in structures comprising a combination of line and via. In this paper, we additionally present leakage and breakdown characteristics of low-k dielectrics in a dual damascene Cu process with via-incorporated interconnect structure scaled to 0.13μm DR. We verify the weak point through BTS (bias temperature stress) assessment in specific structures comprising a combination of line and via. Also, we evaluated the effectiveness of the barrier metal by making a comparison between TaN and TaN/Ta. Lastly, we demonstrate that the result could vary according to the IMD (Inter-metal dielectrics) deposition methodology and integration scheme. We suggest several key processes that can affect leakage reliability degradation and also proper stress condition for meaningful result.
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