Extending gate dielectric scaling limit by NO oxynitride: designand process issues for sub-100 nm technology

摘要

In this work, the characteristics of CMOSFETs with heavilynitrided NO oxynitrides, which meet performance and manufacturabilitycriteria, are investigated. The gate leakage current in NO oxynitridewith sufficient nitridation is reduced by a factor of more than 10 whencompared with thermal oxide of equivalent thickness. It is projectedthat NO oxynitride can be scaled down to an effective physical oxidethickness of 1.5 nm while maintaining strong resistance to B penetrationand low standby power. Significantly enhanced diffusion of B in the Sisubstrate is observed during NO annealing. It is revealed that themagnitude of the diffusivity enhancement strongly depends on the NOannealing temperature, suggesting that the NO anneal process should becarefully optimized to minimize the channel/well dopant redistribution.Additionally, optimum device design for CMOSFETs with heavily nitridedNO oxynitrides is studied. It is experimentally demonstrated thatcareful tailoring of doping profiles for halo and S/D regions isrequired to minimize short-channel device degradation in heavilynitrided devices