Rapid Thermal Chemical Vapor Deposition for Dual-Gated Sub-100 nm MOSFET's

摘要

The main overall goal of this project was to improve the high speed performance of transistors and integrated circuits based on silicon, which is the material on which most microelectronic circuitry (such as microprocessors and memory chips) is based. This project examines the scaling of MOSFET's to very small channel dimensions using a vertical structure which is defined by Rapid Thermal Chemical Vapor Deposition. The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100nm in channel length to be realized. Device operation with a channel length down to 25nm has been achieved.