200 mm process integration for a 0.15 μm channel-length CMOStechnology using mixed X-ray/optical lithography

摘要

An integrated 0.35 μm CMOS technology with 0.15 μm effectivechannel length (L_EFF) is demonstrated in a 200 mm line. X-raylithography is used for the critical gate level, along with conventionaldeep-UV and mid-UV lithography for other levels. Shallow TrenchIsolation (STI) is used to achieve 0.35 μm design rules. The NFET andPFET devices are designed for operation with a scaled power supply of1.8 V. This technology provides 50% performance improvement relative toa 2.5 V, 0.5 μm design rule, 0.25 μm L_EFFhigh-performance CMOS technology