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Local stress engineering for the optimization of p-GaN gate HEMTs power devices

机译:用于优化p-GaN栅极HEMT功率器件的局部应力工程

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The impact of the built-in stress of the SiN passivation layer on p-GaN gate High Electron Mobility transistors (HEMTs) is investigated through TCAD simulations. Local modifications of electron confinement in the channel area due to stressor deposition can be exploited to increase the threshold voltage independently of the ON-state resistance (up to +1.5 V for tsiN = 200 nm, σsin = -2GPa and LG = 0.2 μm). This technique can also be easily combined with an AlGaN back- barrier structure to increase the design margin of p-GaN gate normally-OFF HEMTs.
机译:通过TCAD仿真研究了SiN钝化层的内置应力对p-GaN栅极高电子迁移率晶体管(HEMT)的影响。可以利用由于应力源沉积而在沟道区进行的电子约束的局部修改来增加阈值电压,而与导通状态电阻无关(对于t SiN = 200 nm,σ< sub> sin = -2GPa和L G = 0.2μm)。该技术还可以轻松地与AlGaN背势垒结构结合使用,以增加p-GaN栅极常关型HEMT的设计裕度。

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