IC interconnect transmission line effects due to thecharacteristics of a silicon substrate and crossing metal lines andcurrent return path impedances are physically devised and experimentallycharacterized. Test transmission line patterns having several underlayergeometries are devised and measured for line parameter characteristicsby S-parameter and for signal responses by time domain reflectometry.They are designed and fabricated with a 0.13 μm CMOS DRAM technology.Through this work the effects of underlayer line structures on lineparameter differences and signal distortions are studied. The resultsare useful in gaining a deep understanding of the skew balance ofpackage leads or global signal lines such as clock line andhigh-performance data lines
展开▼
