A Low-Power and Area-Efficient Analog Duty Cycle Corrector for ADC's External Clocks

摘要

This paper presents an analog duty cycle corrector with feedback. A differential charge pump with fast startup is used to detect the duty cycle error and outputs a control voltage for current-starved inverters to adjust the pulse width. The pump current is designed to be adaptive to the input frequency, so a wide frequency range is achieved without requiring a large load capacitor. The circuit is designed in a 130nm CMOS process and can correct 4–100 MHz clocks with 25–75% duty cycle range. The simulation results show that output error is limited to 1.5% and the power consumption is 50 μW at 100 MHz.