CIRCUIT FOR CORRECTING DIGITAL DUTY CYCLE FOR MULTI-PHASE CLOCK AND METHOD FOR THE SAME, ESPECIALLY NOT DEPENDING ON DUTY CYCLE OF INPUT CLOCK

摘要

PURPOSE: A circuit for correcting the digital duty cycle for a multi-phase clock and a method for the same are provided to correct the duty cycle of the overall clock by changing the falling edge of the clock without changing the rising edge of the clock. CONSTITUTION: A circuit for correcting the digital duty cycle for a multi-phase clock includes a rising clock generating unit(120), a falling clock generating unit(130) and a clock delay unit(140). The rising clock generating unit detects the rising edge of the inputted clock and generates the rising edge of the duty cycle correction clock. The falling clock generating unit detects the rising edge of the clock with 180 degrees shift from the inputted clock and generates the falling edge of the duty cycle correction clock. And, the clock delay unit inputs the inputted clock with 180 degree shift into the falling clock generating unit.