adders; cost reduction; delay circuits; logic design; low-power electronics; optimisation; quantum gates; QCA; gate count reduction; generic design; high speed BCD adder optimization design; low power technology; n-bit adders; n-bit subtractors; negative control lines; optical computing; overflow logic detection; processor components; quantum computing; quantum cost reduction; quantum delay reduction; reversible binary adder-subtractor optimization design; reversible logic; Adders; Delays; Heating; Informatics; Logic circuits; Logic gates; Quantum computing; BCD adder; Binary adder/subtractor; Negative controlled Toffoli; Reversible logic;
机译:使用可逆逻辑门的BCD加法器和进位跳过BCD加法器的优化设计
机译:高效可逆BCD加减法架构的设计及其利用进位跳跃逻辑的优化
机译:可逆BCD加法器和跳过BCD加法器的框架以及使用新型可逆逻辑门的量子点元胞自动机的优化
机译:优化可逆二进制加法器/减法器和BCD加法器的设计
机译:浮点FPGA加法器/减法器和乘法器的实现。
机译:面积/延迟优化的早期输出异步全加法器和相对定时的纹波进位加法器
机译:统一单位数字BCD加法器的新型可逆设计
机译:保存加法器和借用子字符设计的确定性程序