Implementation of floating-point FPGA adder/subtractor and multiplier.

摘要

The main idea of this topic is to implement floating-point adder/subtractor and floating-point multiplier by considering model architecture for a reconfigurable device that is specially used to obtain optimization for applications using floating-point operators. Two logics are used for this purpose one is the bit-oriented logic and the other one is the control logic. The parameterization and reconfiguration of word-based coarse-grained units require tables that are word-oriented Look-Up Tables (LUTs) and floating point operations are used to implement data paths.;The alternative block scheme that we use considers virtual blocks embedded on it and it is proposed to model embedded blocks. This is processed with the help of some tools existing in field-programmable gate array. The benchmark circuits are used in the floating point, where the results interpret that the architecture proposed by Chun Hok Ho, ChiWai Yu, Philip Leong et al. can obtain a larger improvement in speed, as large as four times and a large decrease in area when compared to traditional FPGA.