Electronic adder and subtractor for BCD code with decimal display - has parallel operation provided by adder stages coupled to flip=flop array

摘要

The parallel adder or subtractor circuit uses 8421 BCD code and has an output compatable with decimal display. The circuit utilises a number of full adder (VA) and half adder (HA) stages that are formed from Exclusive OR and AND gate logic. Outputs are fed to two series of flip-flops (EF) that connect with a decoding circuit (4,5) to generate the decimal outputs. The one summand is applied in BCD form to one set of inputs (A) and the other set of inputs (B) may be used in conjunction with the flip-flop registers to perform iterative processing.