Parallel adder and subtractor circuit - has adder stages and flip=flop series to provide automatic compensation required for 8421 BCD arithmetic

摘要

The circuit is designed for 8421 BCD operation and has a facility for decimal display. The circuit uses a combination of adder stages with flip-flop registers to handle the necessary correction processor in adding BCD numbers. The processing stage has a number of full adders (VA) and half adders (HA). Outputs are transmitted to two series of flip flops (E,F); with one series (F) providing an accumulator function and linked to one set of inputs (B). In operation the unit automatically accounts for the correction, 6 being included in the computation.