High density low leakage SRAM standby current reduction with a channel stop implant in p-type well in 40nm CMOS development

摘要

In this paper, 32M 0.242um~2 SRAM cell array leakage was reduced significantly by ~ one order of magnitude without affecting the N~+/PW junction capacitance after introducing a channel stop implant (CSI) in P-type well. The space for N~+ in PW to NW is generally much smaller for SRAM than for logic device, therefore SRAM is normally the weakest point for N~+ in PW to NW well isolation. After checking the N~+ in PW to NW leakage, we found that its leakage is the dominant factor for the high SRAM standby current. Furthermore, NMOS performance was also improved with this channel stop implant. The N~+/PW diode, N~+/PW/DNW and P~+/NW/PW bipolar were confirmed to be comparable with the baseline without the channel stop implant. P-type well proximity effect (WPE) and NMOS body effect performance were also analyzed.