Area minimization method for CMOS circuits using constraint programming in ID-layout style

摘要

In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield of LSI chips. In 1D-layout design, the width is shortened by sharing the diffusions and the height corresponds to the number of tracks. In this paper, an area minimization method for CMOS circuits using constraint programming in 1D-layout style is proposed. The experimental results show the effectiveness of the proposed method.