Dry Etching Solutions to Contact Hole Profile Optimization for Advanced Logic Technologies

摘要

As CMOS technology has been continuously scaling down and the dual-stress liner scheme is introduced for simultaneous stress enhancement of both n-MOS and p-MOS, contact etch has started to act as a critical role for the robust performance of integrated circuit. In this work, we investigated the impact of dry etching process on contact hole profile. Results demonstrate the overall contact hole profile can be rigorously controlled if the radio frequency (rf) powers and etching chemistries in inter layer dielectric (ILD) etch step are well balanced. Free local pull-back at contact hole sidewall has to leverage the optimization of etch selectivity of silicon nitride over silicon oxide in liner removal step. Besides, the post etch treatment (PET) is also proven to be imperative for the process window enhancement for such pull-back reduction.