Characteristic Optimization of Single- and Double-Gate Tunneling Field Effect Transistors

摘要

Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (I_D). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 10~(22) cm~(-3), and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (I_(on)/I_(off)) of 5×l0~9 are obtained, compared with the single-gate device.