One critical factor that determines the feasibility of employing carbon nanotubes as channel materials for post-silicon logic devices is the process compatibility to the current CMOS process flow. We show a wafer-scale integration scheme of carbon nanotube field-effect transistor (CNFET) that is performed by 8″ production tools. High density CNT arrays were transferred on the processed wafer, and high performance CNFET with an excellent subthreshold slope (88 mV /decade) is demonstrated. We further show that the work-function tuning enabled by the conventional gate doping can be achieved in our novel embedded poly-Si gate structure. Approximate Vt change of 0.6V, from n-gate to p-gate, is observed. The Vt shift being smaller than the gate work function difference can be attributed to the Fermi level pinning between poly-Si and high-k interface.
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机译:决定采用碳纳米管作为后硅逻辑器件沟道材料的可行性的一个关键因素是与当前CMOS工艺流程的工艺兼容性。我们展示了由8英寸生产工具执行的碳纳米管场效应晶体管(CNFET)的晶圆级集成方案。将高密度CNT阵列转移到处理过的晶片上,并展示了具有出色的亚阈值斜率(88 mV /十倍)的高性能CNFET。我们进一步证明,在我们的新型嵌入式多晶硅栅极结构中,可以实现常规栅极掺杂实现的功函数调整。观察到从n-门到p-门的大约V t inf>变化0.6V。 V t inf>位移小于栅极功函数差,这可以归因于多晶硅和高k界面之间的费米能级钉扎。
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